eASIC
eASIC® is a fabless semiconductor company offering breakthrough NEW ASIC devices that significantly reduce the overall cost of ownership and time to production of customized silicon devices. Through employing a unique combination of FPGA like logic (look up tables) and a single via for routing, eASIC enables customers to develop NEW ASICs with low up-front costs, and deliver of tested prototypes in only 5 weeks from tape out. The NEW ASIC is offered awith a broad portfolio of soft IP including among many others Tensilica Diamond Cores, H.264, DDR2, PCI Express (Gen1 and Gen2), SATA, Fiber Channel and Ethernet MAC.
While the customization technology is innovative and protected by broad patents, the design implementation and device fabrication are performed using conventional electronic design flow and standard manufacturing processes.
The market for custom chips has traditionally been dominated by two technologies, namely FPGAs and standard cell ASICs.
FPGAs provide very low start up costs making them the platform of choice for many prototyping applications. SRAM FPGAs in particular, have gained the lion’s share of the overall market. Packed with SRAM cells and abundant routing, FPGAs provide the designer with a reprogrammable architecture that is well suited for development. However, the silicon overhead required for reprogrammability can be as much as 80% of the overall die size, thereby adding significantly to the device cost and power consumption of the device. Once prototyping is completed designers have sought to move to lower cost solutions such as standard cell ASICs.
Standard cell ASICs utilize two-input NAND gates as the fundamental building blocks. This, coupled with the ability for designers to customize all mask layers makes standard cell the preferred solution for very high volume applications. However, a number of factors have contributed to the rapid demise in the number of standard cell ASIC design starts over the last 10 years. These factors include: exponentially rising mask costs, high priced EDA tools, lengthy design cycles, long manufacturing cycles, expensive sub-micron design expertise and unpredictable ROI. These factors have combined to limit the use of standard cells for all but the highest volume market applications.
eASIC’s innovative architecture delivers a NEW generation of ASIC technology (dubbed NEW ASIC) that makes silicon customization for the masses affordable once more. By replacing SRAM based routing with a scheme that utilizes a single Via provides significant die size reduction over comparable density FPGAs. This in turn results in cost and power savings for designers. The single Via approach also significantly reduces up-front development cost, design and manufacturing time compared to standard cell ASICs. A single via layer requires much less time to validate and manufacture than an all layer standard cell design. With eASIC, designers also need not be concerned with many arduous tasks such as test insertion, clock balancing, ATPG, LVS/DRC, signal integrity analysis, power droop mesh design, tasks that are mandatory for standard cell ASIC design.
eASIC devices are being successfully used by customers all over the world in applications that span from wireless infrastructure to consumer handheld devices. eASIC NEW ASICs are fast becoming the preferred silicon customization solution for production volumes up to approximately one million units per year (depending on application).
Subscribe by RSS